1. Field of the Invention
Example embodiments of the present invention relate generally to a printed circuit board and method thereof and a solder ball land and method thereof, and more particularly to higher resistant printed circuit board and method thereof and a higher resistant solder ball land and method thereof.
2. Description of the Related Art
A printed circuit board (PCB) used as a base frame in a semiconductor package manufacturing process may have adjacent nickel and gold layer surface treatment portions on a solder ball land prepared at the bottom of the PCB. The gold layer may facilitate a fusion of a solder ball, and the nickel layer may have a higher heat conductivity which may allow for greater heat dissipation of heat generated in a semiconductor chip to areas away from the semiconductor chip.
Older conventional solder balls may include a tin and lead compound. Later conventional solder balls, after lead became a disfavored material, may be made to be lead-free. The lead-free solder balls may be used in manufacturing processes of mobile phones and/or other semiconductor package devices so as to increase a durability of the manufactured device (e.g., against possible impacts due to dropping and bending).
Conventional surface treatment process may include organic solderability preservatives (OSP). In an example, an OSP may be used in a surface treatment process for forming a tin-based, lead-free solder ball, a copper solder ball land, and/or an inter-metallic contact (IMC) layer. The OSP may include a higher-adhesive organic glue on the surface of copper that may be used to surface treat a solder ball land surface to reduce or prevent oxidation thereof.
FIG. 1 is a sectional view of a conventional ball grid array (BDA) semiconductor package 50. Referring to FIG. 1, the BGA semiconductor package 50 may include a PCB 20 with connection terminals 16 on a first surface and a solder ball land 12 on a second surface, a semiconductor chip 18 connected to the connection terminals 16 through a gold wire, and a lead-free solder ball 26 connected to the solder ball land 12. Additionally, the ball grid array (BGA) package 50 may include a sealing resin 24 sealing the semiconductor chip 18 and the gold wire 22. The solder ball land 12 may be surface treated with a uniform treating process. A reference numeral 10 may denote an insulating substrate used as a main body of the PCB 20, and a reference numeral 14 may denote a solder resist.
FIG. 2 is a sectional view illustrating the conventional solder ball land 12 of FIG. 1.
FIG. 3 is a sectional view illustrating a process of attaching the lead-free solder ball 26 to the solder ball land 12 of FIG. 2.
Referring to FIGS. 2 and 3, the solder ball land 12 (e.g., portion A of FIG. 1) may include a base copper layer 2, a nickel layer 4 and a gold layer 6. The conventional attachment process of FIG. 3 may include applying solder 9 to the solder ball land 12 formed of the copper layer 2 treated with the nickel layer 4 and the gold layer 6, mounting the solder ball 26 thereon, and attaching the solder ball 26 to the solder ball land 12 through an IR reflow process. Because the gold layer 6 may be thinner than the copper layer 2 and/or the nickel layer 4, the gold layer 6 may dissipate (e.g., may be reduced and/or removed) during the attachment of the solder ball 26 to the solder ball land 12.
Accordingly, an adhering surface (e.g., an adhesive layer such as glue) between the solder ball 26 and the solder ball land 12 may include a metal bonding layer 11 containing a nickel and tin alloy (e.g., after the gold layer 6 may be reduced/removed). The metal bonding layer 11 may have a higher heat conductivity, but also may be associated with lower stress (e.g., shock and/or bending) resistance.
FIG. 4 is a sectional view illustrating another conventional embodiment of the solder ball land 12 of FIG. 1.
FIG. 5 is a sectional view illustrating a process of attaching the lead-free solder ball 26 to the solder ball land 12 of FIG. 4.
Referring to FIGS. 4 and 5, the solder ball land 12 (e.g., portion A of FIG. 1) may include the copper layer 2 as in FIG. 2 with an OSP 28 being applied in place of the gold layer 6 and the nickel layer 4. The conventional attachment process of FIG. 5 may include applying the OSP 28 on the copper layer 2 of the solder ball land 12. A flux 8 may be applied to reduce/remove the OSP 28. The lead-free solder ball 26 may then be attached on the copper layer 2. A metal bonding layer 13 including a copper-tin alloy may be formed in a bonding surface between the solder ball 26 and the solder ball land 12.
The metal bonding layer 13 containing the copper-tin alloy may have a higher durability (e.g., to bending and/or impacts) than the metal bonding layer 11 of FIG. 2, but may also be associated with a lower heat conductivity than the metal bonding layer 11.
Also, because the surface treatment process of FIG. 5 using the OSP 28 may necessitate the additional step of reducing/removing the OSP 28 through the separate flux process (e.g., applying the flux 8 to reduce/remove the OSP 28) during the attachment of the solder ball 26, the fabrication process may increase in complexity, which may likewise increase defects occurring during the surface treatment process of FIG. 5. Such defects may include, for example, a “non-wet” defect. The non-wet defect may be caused, at least in part, because the metal bonding layer 13 may not be formed sufficiently. The metal bonding layer 13 may not be formed sufficiently because the surface of the solder ball land 12 may be deformed by the degradation of the OSP 28 during the application of the flux 8. The non-wet defect may be difficult to detect by visual and/or other non-invasive inspections (e.g., inspections not structurally damaging the solder ball 26), thereby increasing the difficulty of managing the integrity of the surface treatment process of FIG. 5. Accordingly, the reliability of the semiconductor package 50 in FIG. 1 may be reduced.
FIG. 6 is a sectional view illustrating a bonding surface between the solder ball 26 and the solder ball land 12 of FIG. 5. Referring to FIG. 6, the metal bonding layer 13, which may include a copper-tin alloy through the OSP surface treatment, may induce the generation of voids 32 in the copper layer 2 adjacent to the metal bonding layer 13 over a period of time. The metal bonding layer 13 may thereby not be suitable for use in semiconductor packages requiring longer lifespans. The voids 32 may be generated because copper in the copper layer 2 may diffuse into the metal bonding layer 13 (e.g., formed of Cu6Sn5) over the period of time, for example, after the semiconductor package is mounted on a motherboard. The voids 32 may cause degradation to the solder joint reliability (SJR) of the copper layer 2.
Accordingly, the above-described conventional semiconductor packages may not be capable of simultaneously having both a higher resistance to stress (e.g., bending, physical impacts or shocks, etc.) and a higher heat resistance.